DSRC Prototype Testbed
What
is the DSRC/WAVE Prototype Testbed?
What
is the purpose of the DSRC/WAVE Prototype Testbed?
What
makes the DSRC/WAVE Prototype Testbed unique?
Who
is involved in the Prototype development?
Who can I contact for more information?
What is DSRC/WAVE?
Dedicated Short Range Communications (DSRC)/Wireless Access in a Vehicular Environment (WAVE) refers to a set of emerging standards for mobile wireless radio communications. DSRC/WAVE is part of the Federal Highway Authority’s Vehicle Infrastructure Integration (VII) initiative and supports vehicle-to-vehicle (V2V) and vehicle-to-infrastructure (V2I) communications for emerging Intelligent Transportation Systems (ITS). DSRC/WAVE systems fill a niche in the wireless infrastructure by facilitating low latency, geographically local, high data rate, and high mobility communications. The following table compares DSRC/WAVE capabilities to other wireless technologies.
| | DSRC/WAVE | Wi-Fi | Cellular | Mobile
WiMAX5 |
| Data
rate | 3-27Mbps | 6-54Mbps | < 2
Mbps | 1-32 Mbps |
| Latency | < 50ms | Seconds | Seconds | ? |
| Range | < 1km | < 100m | < 10km | < 15km |
| Mobility | > 60 mph | < 5mph | > 60
mph | > 60
mph |
| Nominal
Bandwidth | 10MHz | 20MHz | < 3MHz | <
10MHz |
| Operating
Band | 5.86-5.92GHz
(ITS-RS) | 2.4GHz,
5.2GHz (ISM) | 800MHz,
1.9GHz | 2.5 GHz |
| IEEE
std. | 802.11p (WAVE) | 802.11a | N/A | 802.16e |
Table 1: Comparison of DSRC/WAVE to various wireless systems
What is the DSRC/WAVE Prototype Testbed?
The DSRC/WAVE prototype testbed is a real-time, draft standards conforming prototype wireless networking device. The testbed consists of a digital baseband processor and an analog radio frequency (RF) front-end. The digital baseband processor implements the transmitter, receiver, and front-end control on a single FPGA. The implementers are participating in the IEEE 802.11p OFDM draft standard development and are designing a flexible system capable of adapting to the final adopted standard. The Media Access Controller (MAC) operates on a PowerPC microprocessor embedded on the FPGA. The MAC is being designed according to the IEEE P1609 WAVE trial use standards that are currently being published.
Figure 1: DSRC/WAVE Prototype Testbed hardware architecture
What is the purpose of the DSRC/WAVE Prototype Testbed?
The DSRC/WAVE testbed is being developed to perform conformance testing of 3rd party DSRC/WAVE radios and to provide a platform for development, implementation, and testing of novel wireless algorithms.
What makes the DSRC/WAVE Prototype Testbed unique?
Compared to other wireless testbeds, the Prototype has a unique combination of flexibility, processing power, portability, and price. The FPGA is programmed from within a graphical development environment called Simulink from Mathworks with a Xilinx extension called System Generator. The hardware design is described by a block diagram using System Generator. This block diagram is a fixed-point, cycle-true simulation model that can be synthesized to the hardware. The Prototype hardware design is mirrored by a floating-point model. The floating-point model facilitates fast, floating-point simulations for developing new algorithms. The floating-point and fixed-point sections may interact at any point in the model. This allows fast incremental development of algorithms using a single design architecture for both floating and fixed-point simulations. Among other advantages, the environment enables isolation of algorithms within a floating-point framework to experiment with quantization and delay affects.
Figure 2: Floating-point model of soft-demapper algorithm
Figure 3: Fixed-point model of soft-demapper algorithm
The testbed provides an FPGA with an embedded PowerPC for baseband physical layer and MAC processing. This combination provides programming flexibility and raw processing power that is difficult to match with a homogenous processor or hardware-based system.
The FPGA board itself is designed and produced by Nallatech and sold as the XtremeDSP kit by Xilinx. It consists of a daughter card mounted on a standard PCI expansion card. The RF front-end is contained entirely within a 19" rack mount enclosure. The total physical size of the system will be approximately that of a mid-sized luggage bag. This degree of portability can enable field testing in situations that were impractical before such as the testing of wireless networking algorithms.
Who is involved in the Prototype development?
Development
of the DSRC/WAVE Prototype Testbed is funded by the
Who can I contact for more information?
UCLA
- Jared Dulmage jaredd@ee.ucla.edu
- Minko Tsai minko@ee.ucla.edu
- Dr. Mike Fitz fitz@ee.ucla.edu
- Dr. Babak Daneshrad babak@ee.ucla.edu
UC Berkeley
- Susan Dickey dickey@PATH.Berkeley.EDU
Links and papers
Wintech 2006 demo abstract:
COTS-based DSRC/WAVE Testbed for Rapid Algorithm Development, Implementation, and Test
Wintech 2006 demo presentation:
Wintech 2006 Testbed Presentation
UCLA UnWiReD Lab
http://www.unwired.ee.ucla.edu/
Berkeley/PATH
Nallatech BenADDA FPGA board
http://www.nallatech.com/?node_id=1.2.2&id=27
Xilinx XtremeDSP
http://www.xilinx.com/products/design_resources/dsp_central/grouping/
Xilinx System Generator
http://www.xilinx.com/ise/optional_prod/system_generator.htm
Mathworks Simulink
http://www.mathworks.com/products/simulink/
Acronyms
| CALTRANS | California Department of Transportation |
| DSRC/WAVE | Dedicated
|
| FPGA | Field Programmable Gate Array |
| IEEE | Institute of Electrical and Electronics Engineers |
| ISM | Industrial, Scientific, and Medical |
| ITS-RS | Intelligent Transportation Systems Radio Services |
| MAC | Media Access Control |
| PATH | Partners for Advanced Transit and Highways |
| UnWiReD | UCLA Wireless Research and Development |
| WAVE | Wireless Access in Vehicular Environments |
| V2V | Vehicle-to-Vehicle |
| V2I | Vehicle-to-Infrastructure |